STM32 MCU Internal Architecture Overview (Core Focus)

This article focuses on the internal architecture of STM32 MCUs, providing a firmware developer’s perspective on how the CPU, buses, and peripherals interact.

---

1. Cortex-M CPU Core

Core Responsibilities

The Cortex-M CPU performs three main tasks:

• Fetch: Retrieve instructions from Flash or SRAM
• Decode: Decode instructions
• Execute: Execute instructions

The CPU does not directly control GPIO, I2C, or other peripherals; these are controlled via memory-mapped registers (MMIO).

Core Variants

Core	Features	Suitable Use
M0/M0+	Low power, simple	Basic control
M3	General purpose	Mid-range applications
M4	DSP + FPU	Motor control, audio processing
M7	High performance + Cache	High-speed computation

Note: M4/M7 FPU is single-precision, so float operations are faster than double.

---

2. Memory Architecture (Memory Map)

STM32 maps all memory and peripherals into a 4GB address space:

Address Range	Contents
0x0800_0000	Flash
0x2000_0000	SRAM
0x4000_0000	Peripherals
0xE000_0000	Cortex-M System Control

Concept: The CPU controls peripherals and accesses data by reading/writing these addresses. Example:

GPIOB->ODR |= (1 << 5); // changes actual hardware output

---

3. Bus Architecture

What is a Bus?

A bus is the data channel connecting CPU ↔ memory/peripherals, like a highway. Common STM32 buses:

• AHB (Advanced High-performance Bus): CPU, DMA, SRAM
• APB1 (Advanced Peripheral Bus 1): I2C, USART, Timer
• APB2 (Advanced Peripheral Bus 2): GPIO, SPI, ADC

Bus Matrix

The Bus Matrix allows multiple masters (CPU + DMA) to access peripherals or SRAM simultaneously without conflicts, increasing efficiency.

---

4. Peripheral Architecture

Peripheral Essence

Each peripheral is:

• A hardware state machine
• Controlled via registers

Example: GPIO

• MODER: mode configuration
• ODR: output data
• IDR: input data

Why Enable RCC Clock

RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN;

Without a clock, peripherals do not operate, and writing to registers has no effect.

---

5. Interrupt System (NVIC)

NVIC manages Cortex-M interrupts:

• Priority management
• Nested interrupts
• Fast ISR handling

Interrupt flow:

1. Peripheral event occurs (e.g., RXNE)
2. NVIC evaluates priority
3. CPU jumps to ISR
4. Clear interrupt flag
5. Return to main program

Forgetting to clear flags causes infinite interrupts.

---

6. DMA (Direct Memory Access)

DMA is a “second master” that moves data directly between Peripheral ↔ Memory without CPU intervention. Set it up once, CPU can focus on other tasks, greatly improving efficiency for high-data peripherals like ADC/DAC, UART, and SPI.

---

7. Practical Tips

• CPU executes instructions, peripherals are controlled via registers
• Always enable RCC clock for peripherals
• Understand bus speed differences to avoid unnecessary wait
• Clear interrupt flags to prevent endless loops
• Use DMA to reduce CPU workload for data-intensive operations

Summary: Writing STM32 firmware is fundamentally about understanding the chain: CPU → Bus → Peripheral → Physical Hardware.